The 1-transistor/1-capacitor (1T1C) cell has been the predominant memory cell used in DRAM devices for the last 30 years. Bit density has quadrupled every three years by lithographical scaling and ever increasing process complexity. Maintaining a sufficiently high capacitance value and low transistor leakage current has become a major problem for further scaling.
Alternative DRAM cells have been proposed to overcome the scaling challenges of conventional 1T1C DRAM technology. These alternative DRAM cells are described as follows.
Floating body DRAM (FBDRAM) is a single Metal Oxide Semiconductor Field Effect Transistor (MOSFET) built on either a silicon-on-insulator (SOI) (Okhonin, S., et al. “A SOI capacitor-less 1T-DRAM concept.” SOI Conference, 2001 IEEE International. IEEE, 2001.) or in a triple-well with a buried n-implant (Ranica, R., et al. “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM.” VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on. IEEE, 2004.). The technology has yet to solve its data retention issues, particularly at scaled dimensions.
Various cell designs have been proposed based on the negative differential resistance (NDR) behavior of a pnpn thyristor. An active or passive gate may be used in these designs for trade-offs among switching speed, retention leakage, or operation voltage. The thin capacitively-coupled thyristor (TCCT), as described by U.S. Pat. No. 6,462,359, is a lateral pnpn thyristor constructed on an SOI substrate and has a coupling gate for increased switching speed. Due to its lateral 2D design and the need for a gate, the cell size can be much larger than the 1T1C cell (which is about 6˜8 F2).
Recently, Liang in U.S. Pat. No. 9,013,918 described a pnpn thyristor cell that is constructed on top of a silicon substrate and operated in a forward and reverse breakdown regime for writing data into the cell. The use of epitaxial or chemical vapor deposition (CVD) processed semiconductor layers at the backend of a standard CMOS process adds on thermal cycles and etch steps that may degrade performance and yield of devices already fabricated on the substrate earlier in a fabrication process (e.g., during front-end processing). In addition, pnpn devices operated in the breakdown regime may pose challenges in process control and also power consumption. Additionally, depending on the breakdown mechanism (e.g., tunneling breakdown, avalanching breakdown, etc.) operation in the breakdown regime may pose challenges to long-term reliability of switching and data retention of these memory devices due to physical degradation of component materials.
Therefore, there is a need for a compact cell and array design that is not only small and reliable but also easy for integration and manufacturing.